Hardware Reference
In-Depth Information
i
y
i
zl−
V
y
Y
V
zl−
Z+
MOCCII
V
zm+
i
zm+
i
x
i
zl−
V
x
X
V
zl−
Z−
V
zn−
i
zn−
i
yl+
V
yl+
Y
+
i
z
i
yn+
Z
V
yn−
V
z
MIDCC
i
yl−
V
yl−
Y
−
V
ym−
X
i
ym−
i
x
V
x
Fig. 10.18
The relationship between MIDCC and MOCC
PNP CM
V+
PNP CM
M
18
M
20
M
19
M
12
V
y2
V
y
4
M
3
M
6
V
y1
M
1
X
Z+
Z−
M
4
M
5
M
2
V
y5
V
y3
V
b2
V
b1
M
7
M
8
M
9
M
13
M
14
M
15
V−
NPN CM
Fig. 10.19
An exemplary CMOS implementation of the MIDCC based upon the one proposed by
Horng et al. [
58
]
A typical CMOS implementation of MIDCC employing N number of differen-
tial pairs, current mirrors and current repeater is shown in Fig.
10.19
and appears to
be self-explanatory. When implemented in TSMC 0.35
ʼ
m technology, it exhibited
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