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a
Y
1
Z+
Y
2
FDCCII
Y
3
Z−
Y
4
X+
X−
+V
DD
b
M
8
M
7
M
9
V
bp
M
13
M
2
5
V
bp
I
B
I
x
+
I
x−
I
z
+
I
z−
Y
1
Y
2
Y
4
M
4
M
5
M
6
M
1
M
2
M
3
Z−
X−
Z+
X+
Y
3
M
26
M
12
I
SS
M
10
M
11
V
bn
V
bn
M
24
−V
SS
+V
DD
c
+V
DD
V
bp
V
bp
d
V
bn
V
bn
−V
SS
−V
SS
Fig. 10.13
Symbol of FDCCII and an exemplary CMOS implementation (
a
) The symbolic
notation of FDCCII (
b
) an exemplary CMOS implementation [
38
]; (
c
), (
d
) The details of the
various blocks used in the circuit of Fig.
10.13b
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