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a
N
N
i out
R L
i out
CCIII+
R
i out
X
Z
Y
b
N
i 0
N
B
A
i 0
A
Z
B
R AB
XY
R AB
CCIII−
Fig. 10.6 General configuration for a current processing circuit and output currents [ 6 ]( a ) Output
current flowing to ground ( b ) Floating output current
D ual output CCIII
Z 1
CCII+
CCII+
Y
Z A
Y
Z A
Y
1
2
Z B
X
Z 2
Z B
X
X
Fig. 10.7 Implementation of a dual output CCIII [ 6 ]
i y3 ¼
i x . An exemplary CMOS implementation of the DDCC is
shown in Fig. 10.8 . Other implementations can be devised from existing CMOS
CCII structures such as [ 9 ]. In the circuit of Fig. 10.8 , the two differential stages
composed of M 1 -M 2 and M 3 -M 4 and a current mirror M 5 -M 6 which converts the
0 and as usual i z ¼
 
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