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A
i 1
Y
C
1
V 1
Z+
Y
X
Z+
X
C
X
X
Z+
Z+
i 2
Y
2
Y
V 2
B
D
Fig. 9.17 Electronically-controlled lossless floating inductance derived from the circuit of
Kiranon and Pawarangkoon [ 15 ]
Pawarangkoon [ 15 ] presented two modified FI simulation circuits realizing a
current controlled floating inductance of values L a ¼
CR 1 V T
2 I 0
CR 2 V T
2 I 0 respectively.
It may, however, be noted that there is no restriction on removing both the external
resistors R 1 and R 2 and considering in their place the intrinsic parasitic resistances
of the CCCIIs. When this is done this result in the circuit shown in Fig. 9.17
This version of the circuit simulates a floating inductance between ports 1 and
2 having value
, L b ¼
C
V T
4 I 0
L 1 2 ¼
ð
9
:
16
Þ
If dual outputs CCCIIs are permitted, Yuce et al. [ 16 ] demonstrated that only
three CCCIIs are sufficient to realize a lossless floating inductance along with a
grounded capacitor for both positive inductor and negative inductor. Two such
circuits are shown in Fig. 9.18a, b .
For the circuit Fig. 9.18a , a straight forward analysis shows that its Y-matrix is
given by:
¼
V 1
V 2
I 1
I 2
1
sCR x 1 R x 2 þ
1
1
ð
9
:
17
Þ
11
ð
R x 3
Þ
Therefore, the circuit simulates a positive floating inductance of value L eq ¼
CR x1
(R x2 + R x3 ).
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