Second Generation Controlled Current Conveyors (CCCII) and Their Applications - Current Conveyors: Variants, Applications and Hardware Implementations - page 252

ʼ p W p

L p ʼ n W n

ð 9 : 4 Þ

L n

An analysis of the circuit of Fig. 9.5 gives the characterizing equations of the circuit
as:

i X

V X V Y þ r

ʼ p W p

ð 9 : 5 Þ

q

ʼ n W n
L n

p

2 I B C 0 x

L p þ

1

R x r

ʼ p W p
L p þ

ð 9 : 6 Þ

q

ʼ n W n
L n

p

2 I B C 0 x

where Rx is the transresistance at port-X.
Thus, in this case also, R x is controllable by DC-bias current I B. For further
detailed analysis of this circuit, the reader is referred to [ 3 ]. Several other interesting
CMOS-based CCCII configurations have also been advanced, for instance, see [ 4 - 7 ].
A 2GHz Bi-CMOS CCCII in standard 0.8 m BiCMOS technology was pro-

posed by Seguin and Fabre in [ 8 ] which can be equivalently shown as in the circuit
of Fig. 9.6 .
In this circuit, the signal processing portion is made of only NPN transistor
Q 1 -Q 6 and the DC biasing circuit is composed of a P-MOS repeater and N-MOS

μ

+V

PMOS Current repeater

2 I0

I 0 I 0 I 0

i

2 I0 −i

i z

Q 5

Z

+V

Q 2

Q 1

i x

i

X

I 0

Y

Q 6

I 0

I 0

I 0

Q 4

Q 3

NMOS Current repeater

−V

Fig. 9.6 Bi-CMOS CCCII architecture [ 8 ]