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a
I 1
C 2
V 1
INIC
CCII
C 1
R
CCII
x
I 2
x
z
V 2
y
z
y
b
I 1
C 2
V 1
INIC
I 2
CCII
C 1
R
V 2
CCII
x
x
z
y
z
y
c
I 1
C 2
V 1
INIC
CCII
C 1
R
CCII
x
I 2
V 2
x
z
y
z
y
d
I 1
C 2
V 1
INIC
CCII
I 2
C 1
R
V 2
CCII
x
z
x
y
z
y
Fig. 5.42 Circuit configurations for lossless tunable floating FDNR simulations proposed by
Higashimura and Fukui [ 52 ]
 
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