Hardware Reference
In-Depth Information
Fig. 5.38 Floating FDNR
circuit realization proposed
by Nandi et al. [ 37 ]
CCII+
CCII-
y
x
1
z
y
1
2
z
x
C 2
C 1
R
CCII+
x
z
3
y
2
Fig. 5.39 Lossless floating
FDNR proposed by Nandi
et al. [ 41 ]
CCII+
CCII-
y
1
z
y
1
z
V 1
2
x
C 1
x
C 2
R
CCII+
x
z
3
y
2
V 2
concerned. Analysis leads to the following admittance matrix of this circuit
(Fig. 5.38 ):
1
h 2
h 1
1
s 2 C 1 C 2 R
½ ¼
Y
ð
5
:
47
Þ
h 1
h 1
From the above matrix it can be deduced that all active and passive and sensitivities
of this circuit are very low. It may be noted that if resistors are replaced by
capacitors and the capacitor is replaced by a resistor, the same circuit was shown
in [ 28 ] to realize an ideal floating FDNR.
Another circuit (Fig. 5.39 ) employing exactly the same number of CCs and RC
elements to realize an ideal floating FDNR was subsequently published in 1984
(4 years after the publication of the first ideal floating FDNR in 1980 in [ 28 ]) by
Nandi et al. [ 41 ] for simulating ideal tunable FDNR having value D eq ¼
C 1 C 2 R
where the D eq can be tuned by the only resistor R used in the circuit.
In 1985 Abdalla [ 42 ] commented that by a small modification in the circuit of
Nandi et al. [ 41 ], it becomes possible to employ only one type of CCs i.e. either all
the three CCII
or all the three CCII+. 2 This proposed formulation is shown in
Fig. 5.40 .
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