SATELLITE SYSTEMS - GPS Satellite Surveying - page 79

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Figure 3.10 Simple FBSR.

the GPS week, the P(Y)-codes are reset. Similarly, the C/A-codes are the modulo-2
sum of two 1023 pseudorandom bit codes as follows:

G 1 (t)G 2 t N p ( 10 T) G p (t) = − (3.85)

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G p (t) is 1023 bits long or hasa1msduration at a 1.023 Mbps bit rate. The G p (t)
chip is ten times as long as the X 1 chip. The G 2 -code is selectively delayed by an
integer number of chips, expressed by the integer N p , to produce thirty-six unique
Gold codes, one for each of the thirty-six different P(Y)-codes.
The actual generation of the codes X 1 , X 2 , G 1 , and G 2 is accomplished by a
feedback shift register (FBSR). Such devices can generate a large variety of pseu-
dorandom codes. These codes look random over a certain interval, but the feedback
mechanism causes the codes to repeat after some time. Figure 3.10 shows a very
simple register. A block represents a stage register whose content is in either a one
or a zero state. When the clock pulse is input to the register, each block has its state
shifted one block to the right. In this particular example, the output of the last two
stages is modulo-2 added, and the result is fed back into the first stage and modulo-2
added to the old state to create the new state. The successive states of the individual
blocks as the FBSR is stepped through a complete cycle are shown in Table 3.4. The
elements of the column represent the state of each block, and the successive columns
represent the behavior of the shift register as the succession of timing pulses cause it
to shift from state to state. In this example, the initial state is (0001). For n blocks,
2 n

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0.4
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1 states are possible before repetition occurs. The output corresponds to the state
of the last block, and would represent the PRN code if it were generated by such a
four-stage FBSR.
The shift registers that are used in GPS code generation are much more com-
plex. They have many more feedback loops and they have many more blocks in

−

TA BLE 3.4 Output of FBSR

x 1 0 1 0 0 ··· 1 0 0 0

x 2 0 0 1 0 ··· 1 1 0 0

x 3 0 0 0 1 ··· 1 1 1 0

x 4 1 0 0 0 ··· 1 1 1 1

Output 1 0 0 0 ··· 1 1 1 1