Biomedical Engineering Reference
In-Depth Information
TAble 2.2
Defect Tolerance for Defect-Oblivious and Defect-Tolerant Method for the
Protein Assay
DTI
Value
Assay
Time(s)
Array
Area
(a) p = 0.1
r
f
td
Defect-oblivious method
0.0144
377
10 × 10
0.12
0. 88
1.45
Defect-tolerant method
0.8918
390
10 × 10
0.83
0.17
1.21
DTI
Value
Assay
Time(s)
Array
Area
(b) p = 0.05
r
f
td
Defect-oblivious method
0.0144
377
10 × 10
0.22
0. 78
1.29
Defect-tolerant method
0.8918
390
10 × 10
0.83
0.17
1.09
DTI
Value
Assay
Time(s)
Array
Area
(c) p = 0.01
r
f
td
Defect-oblivious method
0.0144
377
0.30
0.70
1.21
10 × 10
Defect-tolerant method
0.8918
390
0.94
0.07
1.04
10 × 10
For all three values of
p
, defect-aware synthesis results in a higher value
of
r
and a considerably lower
f
. Moreover, the defect-aware biochip design
also provides a much lower value of
td
, which implies that for resynthe-
sized biochips, the performance is compromised much less. Since the
original time cost for the two methods are comparable, the difference in
td
is therefore even more significant. Moreover,
td
falls more sharply for
smaller values of
p
for the defect-aware design. Therefore, for low defect
probabilities, as is often the case for mature manufacturing processes, the
proposed defect-tolerant synthesis method allows resynthesis in the case
of catastrophic defects with lower time-cost increase. This feature is often
required for many biochip applications.
In summary, the incorporation of presynthesis defect tolerance into the
routing-aware synthesis tool leads to a significant improvement in the
robustness of the synthesized design. It also allows the search for an optimal
design under multiple design specifications, including completion time,
chip area, routability, and system dependability.
For the protein assay example, we next run the defect-tolerant routing-
aware and defect-oblivious routing-aware algorithms under a set of combi-
nations of weights in the fitness function. For each combination of weights,
if the derived synthesis result is not routable, the algorithm is repeated until
a routable design is found. Next, we carry out a random defect injection to
each design and obtain its failure rate
f
as defined in Section 2.3. We map each
design G to a 3-D point (
T
G
,
A
G
,
F
G
) where
T
G
,
A
G
, and
F
G
are completion time,
chip area, and failure rate of the design, respectively. Similar to the defini-
tion in Section 2.4.1, a point (
T
G
,
A
G
,
F
G
) is referred to as a
feasibility boundary
point
if there are no other points (
T
m
,
A
m
,
F
m
) such that
T
m
<
T
G
,
A
m
<
A
G
,
and
