Biomedical Engineering Reference
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S 1
S 2
S 1
S 2
Interdependent
modules
distance = 2
Storage
units
D 3
D 1
D 2
D 2
Interdependent
modules
distance = 7
D 1
D 3
Guard ring
Guard ring
(a)
(b)
Figure 2.7
(a) A snapshot of a nonroutable layout from routing-oblivious synthesis (time instant 297 s);
(b) corresponding layout in routing-aware synthesis (time instant 299 s).
distance is minimized, D 3 is placed next to S 1 , and the droplet pathway can
be trivially determined.
Thus, we can see that without violating constraints on time and area
cost, the routing-aware method carefully arranges interdependent modules
close to each other. Therefore, it ensures that droplet pathways can be deter-
mined with a high probability. On the other hand, the routing-oblivious
method only aims to satisfy constraints on time and area cost. As a result,
the interdependent modules are likely to be segregated by other modules
when routing-oblivious synthesis is employed; a consequence of this is that
routing solutions cannot be obtained. Without a careful arrangement of
modules, routing-oblivious synthesis can find feasible routes only if the area
constraint is fairly loose, thereby making enough chip area available to cre-
ate droplet pathways. As a result, time and area cost are compromised, and
the design specifications might not be met.
We examine this issue as follows. We first synthesize the protein assay
under a set of design specifications using both the routing-oblivious and
routing-aware synthesis methods, limits ( T = { T 1 , T 2 , T 3 , , T n }), and a set of
area-cost limits ( A = { A 1 , A 2 , A 3 , …, A n }). Therefore, each synthesized chip
G ij corresponds to a point ( T i , A j ). For each synthesized chip, we check if it
is routable. A point ( Ti , A j ) is referred to as a feasibility boundary point if
there are no other points ( T m , A n ) such that G ij is routable and T m < T i , A n < A j .
A feasibility frontier is defined by connecting all the feasibility boundary
points. Therefore, the feasible design region is defined by the area above
the feasibility frontier. Here, we set T = {320, 340, 360, … 440}. The pool of
design specifications is defined by the Cartesian product of a set of time-cost,
and A = {60, 70, 80, …, 180} and carry out both the routing-oblivious and
routing-aware synthesis (the unit of T is seconds, while the unit of A is mea-
sured in terms of the number of electrodes). The feasibility frontier is derived
for both methods, as plotted in Figure 2.8. Note that in finding the feasibility
frontier, we fix a time limit and search for the minimum chip area for which
a routable synthesis result is available.
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