Biomedical Engineering Reference
In-Depth Information
As shown in Figure 6.11, multiple test droplets are routed in parallel to test
the target transportation pathways separated by five columns (the length of a
well unit, minus one, equals five). In this way, all the transportation pathways
can be covered using one round of column test and one round of row test.
Next, we discuss how this test scheme can be applied when the pin-
constrained design is used. Here we carry out a step-by-step analysis to the
parallel scan-like test procedure described in Chapter 4, Subsection 4.1.1. For
each step in the procedure, we check whether the droplet movement patterns
required in that step are allowed by the pin-assignment layout.
The first step, that is, the peripheral test, involves the routing of a single test
droplet to traverse all the peripheral electrodes. As mentioned in Subsection
6.1.1, the pin-assignment result generated using the Connect-5 algorithm
allows free movement of a single droplet. Therefore, this peripheral test step
can be easily carried out on a pin-constrained chip.
The second step, that is, the column test, requires synchronous routing
of multiple test droplets to traverse every single cell in each column of the
microfluidic array. Note that, here in the multiwell chip design, not every
column of the array is used, and therefore each column needs to be tested.
In fact, it is only every 5th column that is used as a routing pathway, and
so, only a subset of the column test needs to be carried out, as shown in
Figure 6.12. Test droplets are routed to the pseudosources at the beginning of
every 5th column. Next, these test droplets are moved in parallel to traverse
the corresponding column and, finally, routed in sequence to the sink reser-
voir for error detection.
This column test step requires synchronous movement of multiple
test droplets while maintaining a five-column distance. As discussed in
Subsection 6.1.2, while introducing the shuttle-passenger-like well-loading
algorithm, such synchronous movements are allowed by the Connect-5
pin-assignment result.
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Figure 6.12
Parallel scan-like test on a multiwell, pin-constrained chip.
