Biomedical Engineering Reference
In-Depth Information
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Figure 5.8
Pin assignment for the multiplexed assay chip obtained using the testability-aware design
method.
protocol has been modeled by a sequencing graph in Chapter 3, as shown in
Figure 3.37. Mapping the protocol on to the array, chip layout, and schedule has
been obtained as shown in Chapter 3, Figures 3.38 and 3.39, respectively.
Next, we apply the Euler-path-based functional test method to the pre-
ceding chip layout. Again, five iterations of the Euler-path-based functional
test are carried out. The test completion times are shown in Figure 5.9. As in
Figure 5.7, a significant reduction of test completion time is achieved as the
number of electrodes in each test group increases.
Next, we apply the test-aware pin-constrained design method to generate
pin assignment for the chip layout in Chapter 3, Figure 3.38. Pin-assignment
results are generated as shown in Figure 5.10. We use the pin-assignment
result obtained from the test-oblivious broadcast-addressing method for
comparison (see Chapter 3, Figure 3.40).
In Figure 5.10, the pin-assignment result generated from the test-aware
design uses the same number of control pins as the test-oblivious pin-
assignment result from the test-oblivious design method. However, the
test-oblivious result only allows a functional testability of 84%, while the
test-aware result achieves 100%. Combining these results with those from
the multiplexed assay, we can conclude that, by carefully rearranging the pin
assignment, the test-aware design method achieves a significant improve-
ment in chip testability with a trivial increase in the number of control pins.
