PipelinedWormhole Routers - Microarchitecture of Network-on-Chip Routers - page 80

credit
update

outPort outAvailable[0...N-1]

ready out[0...N-1]

CC

RC

SU

en

1

req

outLock 1

SA dst

en

mask

pipeline
register

head

credit update

granted

valid
data

valid
data

ST

Input #i

Output #j

Fig. 5.9 The organization of the router that separates in different pipeline stages SA from ST using
a pipeline register at the output of the SA unit. New requests are generated only when the grants
of the previous requests have been first delivered thus allowing the generation of a new request per
input once every two cycles

0 1 2 3 4 5 6 7 8 9

cc
RC-SA

H LT-BW DQ-ST LT-BW

su

cc
SA-DQ-ST

LT-BW DQ-ST LT-BW

B

cc
RC-SA LT-BW DQ-ST LT-BW

T

su

cc
RC-SA

H LT-BW DQ-ST LT-BW

su

Fig. 5.10 The operation of the pipelined router that delays the delivery of the grants to the input
buffer and the crossbar

to the inputs and the output multiplexers of the router, as shown in Fig. 5.9 .This
organization corresponds to a purely control pipelined organization and faces an
inherent problem. Every flit that requests a certain output at cycle t 0 , it will receive
a grant at cycle t 0 C 1, and should decide how to react in the next cycle. The first
obvious choice is to wait, meaning that a new flit will depart from its input every two
cycles; one cycle spent for the request and one for accepting the grant that appears
one cycle later. While waiting for the grants to come, an input should not send a new
request. To achieve this bevahior the requests produced in the current cycle should
be masked using the grants of the previous cycle (denoted as 'mask' in Fig. 5.9 ). If
the input was previously granted, then the current requests are nullified, thus causing
the arbiter to produce an empty grant vector for this input in the next cycle. Once
the masking logic understands the existence of an empty grant vector it allows the
requests to pass to the arbiter. In this way, a new grant vector is produced every two
cycles thus adding a bubble between any two flits that reach the SA stage.
The behavior of the pipelined router that follows the organization of Fig. 5.9 ,is
depicted in Fig. 5.10 . In this example, the RC stage is considered to be unpipelined.
The head flit that arrives in cycle 0, performs RC and SA during cycle 1 and in