PipelinedWormhole Routers - Microarchitecture of Network-on-Chip Routers - page 76

0 1 2 3 4 5 6 7

cc
SA-DQ-ST

LT-BW RC LT-BW

H

su

cc
SA-DQ-ST

LT-BW LT-BW

B

cc
SA-DQ-ST

T LT-BW LT-BW

su

cc
SA-DQ-ST H LT-BW RC LT-BW

su

Fig. 5.5 The operation of a router that pipelines RC from SA and ST

0 1 2 3 4 5 6 7 8 9 10

cc
SA-DQ-ST

H

LT-BW RC SA LT-BW

su

cc
SA-DQ-ST

LT-BW LT-BW

B

cc
SA-DQ-ST LT-BW LT-BW

su

cc
SA-DQ-ST

T

LT-BW RC LT-BW

su

H

Fig. 5.6 The operation of a pipelined router that executes RC in the first pipeline stage and SA-ST
in the second and exhibits idle cycles due to the unsuccessful switch allocation ( SA )ofthefirst
packet

cycle 1 waits in the buffer, while the tail flit of the same packet arrives in the same
cycle and occupies the next buffer position behind the body flit.
If the SA operation was not successful, either because another input was granted
access to the same output port, or because the output port didn't have enough credits,
the head flit would continue trying. The only effect of such unsuccessful trials would
be to shift the execution example of this input, depicted in Fig. 5.5 some cycles to
the right, as shown in Fig. 5.6 . The SU and CC operations would still take place, but
only for the winner input port that does not experience the idle cycles seen by the
input that lost SA and depicted in Fig. 5.6 .
In cycle 3, of Fig. 5.5 , the head flit moves to the link (LT) and approaches next
router. Now, the body flit is at the frontmost position of the input buffer and performs
SA and CC. The output that was given to the head flit in the previous cycle is
now unavailable for all inputs except this one. Therefore, the request generated
by the body flit would be satisfied for sure since it will be the only active one.
Consequently, in cycle 3 the body flit would be dequeued and switched to the
selected output. The tail flit remains idle waiting its turn to arrive to the frontmost
position of the input buffer.
Assuming that the input buffer is allocated non-atomically, meaning that flits
from different packets can be present at the same time on the same input buffer, the
head flit of a second packet arrives in cycle 3 too. When atomic buffer allocation is
employed, no new flit would arrive at this input, until the buffer is completely empty
from the flits of the previous packet. Implementing atomic buffer allocation in terms
of flow control policy is discussed in Sect. 3.1.2 .