PipelinedWormhole Routers - Microarchitecture of Network-on-Chip Routers - page 71

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Output
Status

input
controller

RC SA

Pipeline
Register

update

Output
Buffer

output buffer
choices

ST

Input Buffer

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FIFO queue

Fig. 5.1 An abstract organization of the single-cycle baseline wormhole router

complicates the operation of the router and introduces idle cycles, as seen by the
flits of each packet, until other dependent operations of previous flits or packets are
completed. The idle cycles imposed by such architectural dependencies are often
called bubbles (empty pieces that flow through the pipeline without doing any actual
work).
Pipelining is not only needed in high-speed configurations but it is also needed
in energy constrained cases that the NoC should be able to sustain an acceptable
operating frequency even under lowered voltage. Scaling the voltage of the circuit is
a useful alternative for increasing energy efficiency and reducing power consump-
tion especially in mobile devices that rely on a battery supply for their operation.
However, lowering the voltage of the circuits increases significantly the delay of
their constituent logic blocks that limits the maximum clock frequency of their
operation. Pipelining retrieves back some of the lost MHz of clock frequency due
to voltage scaling thus keeping a balance between energy efficiency and achievable
performance.
In this chapter, we will describe in detail all the pipelined alternatives for
wormhole routers, their implementation and their runtime characteristics. For the
first time, the pipelined organization of routers is presented in a customizable
manner where pipelining decisions are derived through two basic pipeline prim-
itives: RC and SA pipeline. For each case, the cycle-by-cycle behavior will be
analyzed and any microarchitectural implications that limit the router's throughput
by necessitating the insertion of pipeline bubbles will be discussed and appropriate
solutions will be derived.