Arbitration Logic - Microarchitecture of Network-on-Chip Routers - page 69

a grant or not. The input with the highest priority can be identified by a logical
AND operation of all the per-row priority bits. The input that has all the priority
bits asserted, i.e., PŒi; D 1, receives the lowest priority for the next arbitration
round: PŒi; D 0 and PŒ ;i D 1. With this update the priority of all other
inputs is upgraded by exactly one level.

￿ Hybrid First-Come First Served and Least Recently Used: This priority

update policy, proposed in Boucard and Montperrus ( 2009 ) tries to combine
the benefits of the first-come-first-served and least-recently-used priority-update
policies. When a new request arrives at input i and there is no new request at
input j ,thenPŒi;j D 1. An input is considered to have a new request, when
the request signal changes from 0 to 1 (the detection of this change requires an
edge detector with one extra flip-flop for each request line). If the new request
from input i is not granted in this cycle, the request is not considered new any
more. When, both inputs i and j receive a new request in the same cycle then
their relative priority PŒi;jdoes not change and keeps its old value. At the same
time, when the request of an input i is granted in the previous cycle it receives
the lowest request in this cycle PŒi;j D 0 and PŒj;i D 1.

Any other priority update policy can be derived by changing the priority matrix
taking possibly into account its current state and the status of the grant signals as
depicted in Fig. 4.1 .

4.4 Take-Away Points

The arbiter is responsible for resolving any conflicting requests for the same
resource and it should guarantee that this resource is allocated fairly to the
contenders. The fair allocation of the resources dictates that the arbiter should be
able to change dynamically the priority of the inputs and grant in each arbitration
round the one with the highest priority. Round-robin arbiters as well as arbiter that
store the relative priorities of the inputs in a 2D priority matrix are designed leading
to high-speed logic-level implementations.