Arbitration Logic - Microarchitecture of Network-on-Chip Routers - page 59

Chapter 4
Arbitration Logic

The kernel of each switch module of the router involves arbiter and multiplexer
pairs that need to be carefully co-optimized in order to achieve an overall efficient
implementation. Even if the design choices for the multiplexer are practically
limited to one or two options, the design space for the arbiter is larger. The arbiter,
apart from resolving any conflicting requests for the same resource, it should
guarantee that this resource is allocated fairly to the contenders, granting first the
input with the highest priority. Therefore, for a fair allocation of resources, we
should be able to change dynamically the priority of the arbiter (Synopsys 2009 ).
The organization of a generic Dynamic Priority Arbiter (DPA) is shown in
Fig. 4.1 . The DPA consists of two parts; the arbitration logic that decides which
request to grant based on the current state of the priorities, and the priority update
logic that decides, according to the current grant vector, which inputs to promote.
The priority state associated with each input may be one or more bits, depending on
the complexity of the priority selection policy. For example, a single priority bit per
input suffices for round-robin policy, while for more complex weight-based policies
such as first come first served (FCFS), multibit priority quantities are needed.
In this chapter, we will present the design of various dynamic priority arbiters that
lead to fast implementations and can implement efficiently a large set of arbitration
policies.

4.1 Fixed Priority Arbitration

The simplest form of switch allocators is built using Fixed Priority Arbiters (FPAs),
also known as priority encoders. In this case, the priorities of the inputs are statically
allocated (no priority state is needed) and only the relative order of the inputs'
connections determines the outcome of the arbiter.