Baseline Switching Modules and Routers - Microarchitecture of Network-on-Chip Routers - page 50

asserted when there is one grant bit equal to one. An asserted grant bit means that
the corresponding input has won in arbitration and can move to the selected output.
Concurrently the outLock bit is set to one and the outPort variable is set to the output
port pointed by the head flit. The input buffer receives a ready_in signal that causes
the head flit to be dequeued and transferred to all output ports. However, only one
output multiplexer, driven by its associated arbiter, will select this flit. When the
head flit arrives at the output it de-asserts the outAvailable flag, showing to the rest
inputs that this output port has been allocated and cannot be used by another packet.
AsshowninFig. 3.11 , the rest flits of the packet will check first the outLock Œi
bits. If it is set, they will generate a new request using the stored outPort Œi variable.
For them winning arbitration will be easy since they will be the only flits that will
ask for the output indexed by outPort Œi . Of course, their requests (valid signal of
the input buffer) are also masked with the selected ready signal of the corresponding
output port to guarantee that, when they leave the input, there will be available buffer
space to host them at the output. Once the tail flit reaches the output of the switch it
re-asserts the local outAvailable flag allowing the requesting inputs to participate in
arbitration in the next cycles.
Credit-based flow control does not include any more details than the ones
presented in Sect. 3.3.1 . According to Fig. 3.12 , one credit counter is added per
output that receives the credit updates from the corresponding output buffer and
informs all inputs about the availability of free buffer slots using the ready signal.
Also, each input once it dequeues a new flit it sends backward a credit update.
In many cases, the outputs contain a simple pipeline register, instead of an
output buffer, that just isolates the intra and inter router timing paths. Under this
configuration the design of the switch remains the same. The only difference is
that the credit counter reflects the empty slots available at the buffer at the other
side of the link. As expected, this configuration increases the round-trip time of the
communication between two flow-controlled buffers since the data and the credit

Output #j

outAvailable

credit counter
ready

request

arb

update

grant
valid

valid

data

data

Link

from/to other inputs

Fig. 3.12 The addition of a credit controller per output that may optionally include additional
pipeline registers, allows the connection of the unrolled switching module to multiple independent
credit-based flow-controlled links