Hardware Reference
In-Depth Information
that if the head flit wins arbitration it will find an empty buffer slot at the output.
This request generation procedure is depicted in Fig. 3.7 .
The arbiter receives the requests from all inputs and grants only one. The grant
signals are distributed to all inputs. When the head flit of the i th input wins a grant,
three parallel actions are triggered:
￿The outLock Œi variable is asserted.
￿
A new state variable that is added per input, called outPort Œi , stores the destined
output port indexed by the head flit. This new variable is needed per input since
after the head flit is gone, the body and the tail flits should know which output to
ask for.
￿
The head flit is dequeued from the input buffer by asserting the corresponding
ready_in signal.
The body and the tail flits drive their arbiter requests via their local outPort Œi and
outLock Œi variables. Although the outAvailable flags are checked only by the head
flits, the ready signals are checked every cycle by all flits of the packet. After the
two masking operations - one for availability (only for the head flits) and one for
readiness (for all flits) - are complete a new request is generated for the arbiter. The
arbiter in each cycle can select a different input and move the corresponding flits to
the appropriate output. In the next cycles, the packets from other inputs that will try
to get access to an un-available output port will delete their requests at the request
generation stage and thus only the locked input will be available for that output.
3.3.1
Credit-Based Flow Control at the Output Link
Under credit-based flow control, the inputs before sending any flits to their selected
output should guarantee that there are available credits at that output. If this is
true when a flit leaves the input buffer and moves to the output it consumes one
credit from the appropriate credit counter. The implementation of credit-based flow
control requires the addition of one credit counter for each output placed at the
output of the switching module, as shown in Fig. 3.8 . The credit counter reduces
the available credits every time a new valid flit reaches the output and increases the
available credits once an update signal arrives from the corresponding output buffer.
Multiple credit updates can arrive in each cycle, each one referring to a different
output buffer. Ready signals (one for each output) that declare credit availability, i.e.,
creditCounter Œi > 0, are generated by the counters at the output of the switching
module and distributed to all inputs.
Equivalently the input buffers when they dequeue a new flit they are obliged to
send backwards a credit update according to the credit-based flow-control policy.
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