Baseline Switching Modules and Routers - Microarchitecture of Network-on-Chip Routers - page 37

IP

arb

Link

data

IP

mem
ctrl

memory

valid

ready

IP

sender receiver

Fig. 3.1 Sharing a memory controller to multiple cores of the chip

The arbiter that drives the select signals of the multiplexer is a sequential
circuit that receives the requests from the inputs and decides which input to grant
based on its internal priority state. The priority state keeps track of the relative
priorities of the inputs using one or more bits depending on the complexity of
the priority selection policy. For example, a single priority bit per input suffices
for round-robin policy, while for more complex weight-based policies, such as
firstcome- first-served (FCFS) or age-based allocation, multi-bit priority state is
required. Round-robin arbitration logic, which is the most widely applied policy
and the easiest to implement, scans the input requests in a cyclic manner beginning
from the position that has the highest priority and grants the first active request. On
the next arbitration cycle, the position that was granted receives the lower priority.
The design details involved in arbiter design can be found in Chap. 4 .
In this chapter, we begin our discussion on switching with the simple example
of many inputs sending data to a shared output via a common link and next we will
describe how this simple design can evolve gradually to support multiple outputs,
thus actually deriving a fully fledged NoC router.

3.1 Multiple Inputs Connecting to One Output

The design of a multiple-input to one output connection besides arbitration should
take also into account the output flow control mechanism for guaranteeing that the
flits leaving from each input will find the necessary buffer space in the shared output.
Without loss of generality we assume that each input is attached to the switching
module (arbiter and multiplexer) via a buffer that respects the ready/valid handshake
protocol. The same holds for the output. The output buffer accepts the valid and the
associated data from the output multiplexer and returns to all inputs one ready signal
that declares the availability of buffer space at the output. The buffers at the inputs
and outputs can be either simple 1-slot EBs, or 2-slot ones or even larger FIFOs
that can host many flits. An abstract organization of the multiple-input-one-output
connection is shown in the left upper side of Fig. 3.2 .