Hardware Reference
In-Depth Information
data take their place and some upper-level protocol should care for retrieving the lost
data. Dropping in a NoC environment is of limited importance since the complexity
involved in retrieving the lost data is not substantiated by the hardware savings of
bufferless flow control; if the buffering cost at the sender or the receiver cannot
exceed the cost of one register, 1-slot EBs (or a 2-slot EB implemented with latches)
can be used that allow for lossless and full throughput operation.
2.7
Wide Message Transmission
On-chip processing elements may need to exchange wide piece of information.
Transferring wide messages in a single cycle may require close to thousands of wires
between a sender and a receiver. Such amount of wiring is hard to handle especially
in the case of an automated placement and routing design flow that performs routing
in an unstructured row-based substrate of placed gates and registers. Besides the
physical integration challenges that such wide links may cause, their utilization will
always be under question. In real systems a variety of messages is transferred from
time to time. Small memory request messages can be of the order of tens of bytes
or less, while long reply messages can carry hundreds of bytes. Therefore, making
the links equally wide to the largest message that the system can support is not a
cost effective solution and would leave the majority of the wires undriven most of
the time. Common practice keeps the link width close to the width of the most
commonly used message that is transferred in the system and impose the larger
messages to be serialized and pass the link in multiple clock cycles.
Wide messages are organized as packets of words. The first word, called
the header of the packet, denotes the beginning of the packet and contains the
identification and addressing information needed by the packet, including the
address of its source and its destination. The last word of the packet is called the
tail word and all intermediate words are called the body words. Each packet should
travel on each link of the network as a unified entity since only the header of the
packet carries all necessary information about the packet's source and destination.
To differentiate from the words of a processor, the words that travel on the network
are described with the term flit (derived from flow-control digit). An example packet
format is depicted in Fig. 2.19 .
Figure 2.19 depicts the wires needed in a network-on-chip channel that supports
many flit packets. Besides data wires and necessary flow control signals (ready/valid
is used in this example) two additional wires, e.g., isHead and isTail are needed that
encode the type of the flit that traverses the channel per cycle. isHead and isTail
signals are mutually exclusive and cannot be asserted simultaneously. When they
are both inactive and valid = 1, it means that the channel holds a body flit.
Figure 2.20 depicts the transmission of two 4-flit packets over 3 links separated
by 2 intermediate nodes. During packet transmission, when an output port is free
the received word is transferred to the next output immediately without waiting the
rest words of the packet, i.e., flit transmission is pipelined. The transfer of flits on
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