Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 22

buffer slots of the receiver. The number of available slots is called credits and they
are stored at the sender side in a credit counter. When the number of credits is larger
than zero then the sender is allowed to send a new word consuming one available
credit. At each new transmission the credit counter is decremented by one reflecting
that one less buffer slot at the receive side is now available. When one word is
consumed at the receive side, leaving the input buffer of the receiver, the sender is
notified via a credit update signal to increase the available credit count.
An example of the operation of the credit-based flow control is shown in
Fig. 2.13 . At the beginning the available credits of the sender are reset to 3 meaning
that the sender can utilize at most 3 slots of the receiver's buffer. When the number of
available credits is larger than 0 the sender sends out a new word. Whenever the sink
of the receiver consumes one new word, the receiver asserts a credit update signal
that reaches the sender one cycle later and it increases the credit counter. The credit
updates, although arrive with cycle delay, they are immediately consumed in the
same cycle. This immediate credit reuse is clearly shown in the clock cycles where
the available credits are denoted as 0*. In those clock cycles, the credit counter that
was originally equal to 0 stays at 0, since, it is simultaneously incremented due to
credit update and decremented due to the transmission of a new word. When the
words are not drained at the sink they are buffered at the receiver. No word can be
dropped or lost since each word reaches the receiver after having first consumed
the credit associated with a free buffer position.

2.5 Pipelined Data Transfer and the Round-Trip Time

When the delay of the link exceeds the desired clock period we need to cut the
link to smaller parts by inserting the appropriate number of pipeline registers. In
this case, it takes more cycles for the signals to propagate in both the forward and
the backward direction. This may also happen when the internal operation of the
sender and the receiver, requires multiple cycles to complete as done in the case of
pipelined routers that will be elaborated in the following chapters.
An example of a flow-controlled data transmission over a pipelined link is shown
in Fig. 2.14 , where the valid and ready pass through the pipeline registers at the
middle of link before reaching the receiver and the sender, accordingly. The sender,
before sending new data on the link by asserting its valid signal, should check its
local ready signal, i.e., the delayed version of the ready generated by the receiver. 1
If the sender asserted the valid signal irrespective the value of the incoming ready
signal, then either the transmitted words would have been dropped, if the receiver's
buffer was full, or, multiple copies of the same data would have been written in
the receiver, if buffer space was available. The second scenario occurs because the
sender is not aware of the ready status of the receiver and it does not dequeue the
corresponding data.