Link-Level Flow Control and Buffering - Microarchitecture of Network-on-Chip Routers - page 11

Chapter 2
Link-Level Flow Control and Buffering

The simplest form of a network is composed of a single link with one sender and one
receiver. In parallel to the data wires, the sender and the receiver need to exchange
some extra information that will allow them to develop a common understanding on
the intentions of each side. Figure 2.1 a shows a sender and a receiver that besides
the data wires drive two extra wires, a ready and a valid bit, that are responsible for
co-ordinating the flow of data from one side to the other.
When the sender wants to put new data on the link it asserts the valid signal. The
receiver samples new data from the link only when it sees valid D 1. If the sender

wants to stall transmission it just drives the valid signal to 0.
Equivalently, at the other side of the link, the receiver may stall too. If the sender
is not aware of the receiver's stall, it will provide new words on the link that will not
be sampled by the receiver and destroyed by the subsequent words transmitted by
the sender. Therefore, a mechanism is required that will inform the sender for the
receiver's availability to receive new words. This is achieved by the ready signal.
Any communication takes place only when the receiver is ready to get new data
(ready

D 1) and the sender has actually sent new data (valid D 1). When the receiver

is not ready (ready 0), the data on the link are not sampled and they should not

change until the receiver resumes from the stall. The sender locally knows that when
valid

D

1 the transmitted work is correctly consumed by the receiver
and can send a new one.
The different values of the ready/valid signals put the link, between the sender
and the receiver, in three possible states:

D 1 and ready D

￿ Transfer: when valid 1, indicating that the sender is providing

valid data and the receiver is accepting them.

D 1 and ready D

￿ Idle: when valid 0, indicating that the sender is not providing any valid data,

irrespective the value of the ready signal.

D

￿ Wait: when valid 0, indicating that the sender is providing data

but the receiver is not able to accept it. The sender has a persistent behavior and
maintains the valid data until the receiver is able to read them.

D 1 and ready D