Hardware Reference
In-Depth Information
1.5
Putting It All Together
Initially assume that the CPU of the example system shown in Fig. 1.7 wants to
read from an address that is stored in a memory in the other side of the chip. The
NI of the CPU packetizes the read transaction including all the necessary control
and addressing information that will allow the read request of the CPU to reach
the memory controller. The NI acting as a packet source sends the read request
packet to the first router. The router parses the header of the packet and understands
to which output it should forward the incoming packet. Assuming that no other
packet wants to leave from the same output and there is buffer space available to
the next router, the first router forwards the packet to the next router. The following
router will execute exactly the same tasks and finally the packet will reach the NI
of the memory (RAM). The NI of the RAM parses the incoming packet and presents
the read transaction to the slave memory controller. The memory (slave) produces
the requested data and tries to send it back to the master that requested them. The
NI of the RAM packetizes the reply data and using the network of routers allows
the reply packet to reach the NI of the CPU (master). The CPU gets the necessary
data in the appropriate interface of the transaction-layer protocol.
Using this network of routers multiple transactions could have completed in
parallel between different master and slave pairs. When two or more packets
want to move using the same link, the router solves the contention and serializes
appropriately the requesting packets.
As in any network, the fundamental operation of a NoC is based on protocol
layering that allows the decomposition of the network's functionality to simpler
tasks, hides the implementation details of each layer and enables the network
resources to be shared by allowing multiple transactions to execute on the same
communication medium.
Following Fig. 1.8 , each layer of the network acts as a service provider to the
higher layers while it acts as a service user of the lower layers. Each layer can
be implemented, optimized, and upgraded independently from the other layers
thus allowing for maximum flexibility at network design and SoC integration
phases. The main benefit of this layered design approach is that multiple different
implementations of a layer can exist depending on the application domain and the
ACC
NI
NI
RAM
ACC
NI
NI
CPU
CPU
NI
NI
DSP
Fig. 1.7
Transfer of information across the network between two system's cores
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