Introduction to Network-on-Chip Design - Microarchitecture of Network-on-Chip Routers - page 8

1.4.2 The Network: The Physical Layer

The packets generated by the NIs reach their destination via a network of routers and
links that are independently flow-controlled and form an arbitrary topology (Balfour
and Dally 2006 ; Kim et al. 2007 ). Each router, in parallel to the network links, can
connect to one or multiple NIs thus allowing to some of the cores of the system to
communicate locally without their data to enter the network (Kumar et al. 2009 ).
At the network, the main issues that need to be resolved is handling connectivity
and contention. Connectivity means that any two IP cores connected to the network
via their NIs should be able to exchange information irrespective of their physical
placement on the chip. Contention on the other hand is the result of offering
connectivity via shared channels. Handling contention at the physical layer requires
arbitration, multiplexing and buffering. In the example shown in Fig. 1.6 ,many
IP cores are eligible to access the memory controller (RAM). However, in each
clock cycle only one of them will actually transfer its data to it. The selection of
the winning IP core is done by the arbitration logic and the movement of data is
done via the switching multiplexers that exist inside each router. The IPs that lost in
arbitration keep their data/packets in local buffers waiting to be selected in the next
arbitration rounds.
While link-level flow control enables lossless operation across a sender and a
receiver in a one-to-one connection, and arbitration and multiplexing enable sharing
a link by many peers, real networks involve more complex switching cases that
involve many to many connections. Each router should concurrently support all
input-output permutations and solve the contention to all outputs at once respecting
also the flow-control policy of the output links. Establishing a path between any
source and destination of a complex network topology is a matter of the routing
algorithm that is either implemented completely at the NIs or by the routers in a
step-by-step and distributed manner.

Link

ACC NI

NI RAM

ACC NI

NI CPU

CPU NI

NI DSP

Router

Fig. 1.6 A network-on-chip consisting of routers and links that reach the system's modules via
the network interfaces ( NI )