Hardware Reference
In-Depth Information
Mishra A, Vijaykrishnan N, Das CR (2011) A case for heterogeneous on-chip interconnects for
cmps. In: Proc. of the intern. symp. on Computer architecture, ISCA '11, pp 389-400
Moscibroda T, Mutlu O (2009) A case for bufferless routing in on-chip networks. In: Proceedings
of the 36th International Symposium on Computer Architectur, IEEE
Mukherjee SS, Silla F, Bannon P, Emer J, Lang S, Webb D (2002) A comparative study of
arbitration algorithms for the alpha 21364 pipelined router. In: International Symposium on
Architectural Support for Programming Languages and Operating Systems
Mullins R, West A, Moore S (2004) Low-latency virtual-channel routers for on-chip networks. In:
Proceedings of the International Symposium on Computer Architecture, IEE, pp 188-197
Nachiondo T, Flich J, Duato J (2006) Destination-based hol blocking elimination. In: International
Conference on Parallel and Distributed Systems, IEEE Computer Society, pp 213-222
Ni N, Pirvu M, Bhuyan LN (1998) Circular buffered switch design with wormhole routing and
virtual channels. In: ICCD, pp 466-473
Nicopoulos C, et al (2006) Vichar: A dynamic virtual channel regulator for network-on-chip
routers. In: IEEE/ACM Intern. Symp. on Microarchitecture, pp 333-346
Park J, O'Krafka B, Vassiliadis S, Delgado-Frias J (1994) Design and evaluation of a damq multi-
processor network with self-compacting buffers. In: Proceedings of the 1994 ACM/IEEE Con-
ference on Supercomputing, IEEE Computer Society Press, Supercomputing '94, pp 713-722
Passas G, Katevenis M, Pnevmatikatos D (2010) A 128 x 128 x 24gb/s crossbar interconnecting
128 tiles in a single hop and occupying 6% of their area. In: Fourth ACM/IEEE International
Symposium on Networks-on-Chip (NOCS), pp 87-95
Peh LS, Dally WJ (2001) A delay model and speculative architecture for pipelined routers. In: Proc.
International Symposium on High-Performance Computer Architecture (HPCA), pp 255-266,
URL http://portal.acm.org/citation.cfm?id=876446
Rahimi A, Loi I, Kakoee MR, Benini L (2011) A fully-synthesizable single-cycle interconnection
network for shared-l1 processor clusters. In: DATE, pp 1-6
Ramabhadran S, Pasquale J (2003) Stratified round robin: a low complexity packet scheduler with
bandwidth fairness and bounded delay. In: SIGCOMM '03: Proceedings of the 2003 conference
on Applications, technologies, architectures, and protocols for computer communications,
ACM, New York, NY, USA, pp 239-250, DOI http://doi.acm.org/10.1145/863955.863983
Rao S, Jeloka S, Das R, Blaauw D, Dreslinski R, Mudge T (2014) Vix: Virtual input crossbar
for efficient switch allocation. In: Proceedings of the The 51st Annual Design Automation
Conference on Design Automation Conference, DAC '14, pp 103:1-103:6
Roca A, Flich J, Dimitrakopoulos G (2012) Desa: Distributed elastic switch architecture for effi-
cient networks-on-fpgas. In: 22nd Inter. Conf. on Field Programmable Logic and Applications
(FPL), pp 394-399
Saponara S, Bacchillone T, Petri E, Fanucci L, Locatelli R, Coppola M (2014) Design of an noc
interface macrocell with hardware support of advanced networking functionalities. IEEE Trans
Computers 63(3):609-621
Satpathy S, Das R, Dreslinski RG, Mudge TN, Sylvester D, Blaauw D (2012) High radix self-
arbitrating switch fabric with multiple arbitration schemes and quality of service. In: The 49th
Design Automation Conference 2012, DAC '12, pp 406-411
Seitanidis I, Psarras A, Dimitrakopoulos G, Nicopoulos C (2014a) Elastistore: An elastic buffer
architecture for network-on-chip routers. In: Proc. of Design Automation and Test in Europe
(DATE)
Seitanidis I, Psarras A, Kalligeros E, Nicopoulos C, Dimitrakopoulos G (2014b) Elastinoc: A self-
testable distributed vc-based network-on-chip architecture. In: International Symposium on
Networks-on-Chip (NOCS)
Synopsys (2009) Arbiter with dynamic priority scheme. DesignWare Building Block IP URL
www.synopsys.com
Take Y, Matsutani H, Sasaki D, Koibuchi M, Kuroda T, Amano H (2014) 3d noc with inductive-
coupling links for building-block sips. Computers, IEEE Transactions on 63(3):748-763
Tamir Y, Chi HC (1993) Symmetric crossbar arbiters for VLSI communication switches. IEEE
Transactions on Parallel and Distributed Systems 4(1)
Search WWH ::




Custom Search