Hardware Reference
In-Depth Information
0
1
2
3
4
5
6
7
cc
H0
LT-BW
RC-EB
VA
SA-DQ-ST
LT-BW
su
cc
B0
EB
SA-DQ-ST
LT-BW
LT-BW
cc
T0
LT-BW
EB
SA-DQ-ST
LT-BW
su
cc
H1
LT-BW
RC-EB
V su
SA-DQ-ST
LT-BW
Fig. 9.14 An example of the operation of the 3-stage pipelined router RC|VA|SA-ST for the flits
of two packets arriving at VC#0 and VC#1 respectively
role of pipelined registers at each stage. In all cases, the bypass paths used for the
head flits have been removed and outPort Œi as well as outVC Œi and outVCLock Œi
are first written in one cycle and their values move to the next pipeline stage in the
next cycle.
An example of the router's cycle-by-cycle operation is illustrated in Fig. 9.14 .
The first flit is written at input VC#0 buffer in cycle 0 and appears at its frontmost
position in cycle 1. The EB in front of the queue is currently empty, so the head
flit can occupy it, as it performs RC and writes its result in outPort Œ0 register.
From that point, it requests any available output VC from the output port pointed
by the outPort Œ0 variable. The VA returns one available output VC, and the id of
the allocated output VC is stored at the outVC Œ0 register at the end of cycle 2.
In cycle 3, the head flit is granted in SA, gets dequeued from the EB and reaches
the output pipeline register, while consuming a credit from its allocated output VC.
Since the EB will become empty in cycle 3, the combinational ready propagation
of the pipelined EB allows the body flit to get written in the same cycle in the
intermediate EB, thus leaving the frontmost position of the input VC#0 buffer for
the tail flit. In parallel, a head flit of another packet arrives at the same input that
belongs in VC#1.
In cycle 4, three flits are active. The body flit, which wins in SA and is dequeued
from the EB to reach the output; the tail flit behind it, that is written to the
intermediate EB, and the head flit, which moves to the intermediate EB of input
VC#1 after computing its destined output port and saves the result in outPort Œ1.
As the tail flit of input VC#0 is granted in SA and releases its output VC, input
VC#1 allocates a different output VC using VA. In cycle 6, while the tail flit of the
first packet crosses the link, the head flit that arrived in VC#1 succeeds in SA, gets
dequeued from the intermediate EB and moves to the selected output. Unless the two
incoming packets were heading to the same output VC of the same output port, the
flit flow remains uninterrupted. Of course, if the two packets had arrived in the router
using the same input VC, a bubble would be unavoidable, due to characteristics of
the pipeline after the VA stage.
 
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