Introduction to Network-on-Chip Design - Microarchitecture of Network-on-Chip Routers - page 2

the physical and logical medium for any kind of data transfer and its latency,
bandwidth and energy efficiency directly affects overall system performance.
Interconnect design is a multidimensional problem involving hardware and software
components such as network interfaces, routers, topologies, routing algorithms and
communication programming interfaces.
Modern heterogeneous multiprocessing systems have adopted a Network-on-
Chip (NoC) technology that brings interconnect architectures inside the chip. The
NoC paradigm tries to find a scalable solution to the tough integration challenge
of modern SoCs, by applying at the silicon chip level well established networking
principles, after suitably adapting them to the silicon chip characteristics and to
application demands (Dally and Towles 2001 ; Benini and Micheli 2002 ;Arteris
2005 ). While the seminal idea of applying networking technology to address
the chip-level interconnect problem has been shown to be adequate for current
systems (Lecler and Baillieu 2011 ), the complexity of future computing platforms
demands new architectures that go beyond physical-related requirements and
equally participate in delivering high-performance, quality of service, and dynamic
adaptivity at the minimum energy and area overhead (Bertozzi et al. 2014 ; Dally
et al. 2013 ).
The NoC is expected to undertake the expanding demands of the ever increasing
numbers of processing elements, while at the same time technological and appli-
cation constraints increase the pressure for increased performance and efficiency
with limited resources. Although NoC research has evolved significantly the last
decade, crucial questions remain un-answered that call for fresh research ideas and
innovative solutions. Before diving in the details of the router microarchitecture that
is the focus of this topic, we will briefly present in this chapter the technical issues
involved in the design of a NoC as a whole and how it serves its goal for offering
efficient system-wide communication.

1.1 The Physical Medium

The available resources that the designer has at the physical level are transistors and
wires. Using them appropriately the designer can construct complex circuits that
are designed at different abstraction levels, following either custom or automated
design methodologies. Interconnect architectures should use these resources in the
most efficient manner offering a globally optimum communication medium for the
components of the system.
The wires are used as the physical medium for transferring information between
any two peers. On-chip wires are implemented in multiple metal layers that are
organized in groups (Weste and Harris 2010 ),asshowninFig. 1.1 . Each group
satisfies a specific purpose for the on-chip connectivity. The first metal layers are
tailored for local connectivity and are optimized for on-chip connections spanning
up to several hundreds of m. They offer highly dense connections that allow
thousands of bits to be transferred in close distance. Upper metal layers, are built