Pipelined Virtual-Channel-Based Routers - Microarchitecture of Network-on-Chip Routers - page 149

0 1 2 3 4 5 6 7

CC
VA-SA-DQ-ST
SU

H

LT - BW RC LT - BW

CC

B

LT BW LT BW

SA-DQ-ST

CC
SU

T

LT - BW SA-DQ-ST LT - BW

CC
VA-SA-DQ-ST
SU

H

LT - BW RC LT - BW

Fig. 9.5 An example of the operation of a 2-stage pipelined router that executes RC in the first
pipeline stage and VA-SA-ST in the next, for the flits of two packets that arrive at the same input
VC. The pipeline registers after RC are placed only in the control path of the router

is executed in cycle 1 and the result is stored in outPort register (and possibly in
candidateOutVC register). In parallel, a body flit arrives at the input VC buffer and
remains behind the head flit in the same queue. Thus, the body flit is unable to
execute any operation in cycle 2, since the head flit has not been dequeued yet. The
head flit is dequeued in cycle 2 after having successfully performed all the required
tasks. The dequeue of the head flit brings the body flit to the frontmost position of the
input VC buffer. The body flit uses the values stored in outPort and outVC variables
to issue a request to SA in cycle 3. The body flit, once granted, gets dequeued and
traverses the crossbar heading to the appropriate output port. The same applies for
the tail flit that follows that also releases the per-packet allocated resources, when it
moves to the output of the router (SU just after ST).
The head flit of the next packet, that waited the departure of the tail flit in cycle
4, manages to perform RC in cycle 5, and finally use the selected output port in
cycle 6. Observing the router's incoming and outgoing traffic under this scenario,
the router's outputs always remain idle after a tail flit, whatever the next packet's
destination might be. This idle cycle would never appear if the following packets
belong to different input VCs, of the same or a different input port.

9.2.2 Pipelining the Router in the Control and the Data Path

When the pipeline register after RC is placed only in the control path, the head flit
of a packet cannot perform RC, even if no flit is using the RC unit, until it reaches
the frontmost position of the corresponding input VC buffer. Allowing the head flit
to perform RC, while the tail of another packet in the same input VC performs SA
and ST, requires adding an extra pipeline register at the datapath of the VC-based
router. This pipeline register is in fact a 1-slot pipelined elastic buffer (EB) that
participates in the flow control mechanism and can be seen as an extension of the
input VC buffer. In this way, every flit that reaches the frontmost position of the
input buffer moves to this intermediate EB (if it is not full) and from there performs
the rest tasks of the VC-based router. A head flit while moving to the intermediate
EB performs RC and updates the outPort Œi and possibly the candidateOutVC Œi
pipeline registers. In this way, once the tail flit reaches the frontmost position of the