Pipelined Virtual-Channel-Based Routers - Microarchitecture of Network-on-Chip Routers - page 145

ready bits of the credit counters are distributed to all input VCs of the router thus
informing them about the availability and the readiness of the VCs of all output
ports. Each input VC for generating the corresponding requests to VA or to SA
checks the values of those bits as well as the corresponding local state variables
The allocation decisions taken for each packet during VA or for each flit during
SA, update effectively the state of each output VC both in terms of availability as
well as credit readiness. Therefore, every head flit that gets allocated to an output
VC during VA should in parallel update the state of the selected output VC (State
Update - SU), thus reflecting that it is currently occupied. Equivalently, when the
tail flit of the same packet is granted from SA and prepares to leave the router,
should release the allocated output VC, thus enabling its re-use by other packets of
the same or another input VC.
In a similar manner, every flit that is granted during SA and gets switched by the
crossbar (switch traversal - ST) should decrement the appropriate credit counter of
the selected output. According to Fig. 9.1 , this credit consumption (CC) is done just
after ST but in the same cycle. Implementing CC earlier, after or in parallel to SA,
as done in pipelined WH routers in Chap. 5 , is not easy. In VC-based routers, each
flit, once granted, should transfer to the credit counters the id of the allocated output
VC, in order to ensure that the correct counter is decremented. The transfer of the
output VC id to the credit counters actually requires a complete crossbar similar to
the one available in ST but of less bits (it should transfer only the output VC id of the
winning flit). Therefore, since ST already switches all the fields of a flit, including
its output VC id, there is no reason to add a second crossbar for implementing CC
earlier than normal ST. The following paragraphs present two running examples of
the operation of a single-cycle VC-based router that illustrate how the presented
operations evolve in time.

9.1.1 Example 1: Two Packets Arriving at the Same Input VC

The operations executed per-cycle by a single-cycle VC-based router are illustrated
in Fig. 9.2 . The diagram presents the behavior of a single input VC that receives
a 3-flit packet (head, body and tail) in consecutive cycles. Due to the interleaving
of flits among different VCs on the same input, this type of burst traffic may not
always be representative for a VC router. Irrespective of that, the un-interrupted
service of a packet arriving from an input VC, when the network is almost idle,
is a requirement for every NoC design. In the following examples, we assume that
a packet is not limited to which output VCs it can request; it is allowed to ask
for any available output VC of its destination. Whenever this assumption conceals
pipelining inefficiencies, it will be stated explicitly.
The head flit arrives from an input link (LT) and is written at an input VC
buffer (BW) in cycle 0. In cycle 1, it appears at the frontmost position of the
corresponding input VC buffer. The RC unit, dedicated to that input VC, reads the
packet's destination from the flit's header and calculates the requested output port.