High-Speed Allocators for VC-Based Routers - Microarchitecture of Network-on-Chip Routers - page 135

a

Output VC selection Local Arbitration Global Arbitration

outVCAvailable

granted[i]

ready VC

V:1
arb

reqPort[i]

N

V V

N:1
arb

N

V:1
arb

V

N

V

reqVC[i] V

per input VC local MUX

selec

N:1
arb

per input port

b

Output VC selection

outVCAvailable

ready VC

per input VC

reqPort[i]

N

V V

Global Arbitration

V:1
arb

V

V

V

reqVC[i] N:1

arb

deMUX

N N

N:1
arb

Local Arbitration

per input port

V:1
arb

granted[i]

c

Output VC selection

outVCAvailable

ready VC

per input VC

reqPort[i]

LVA1
nextReqVC[i]

N

V V

Global Arbitration

V

V

V

reqVC[i] N:1

arb

deMUX

N N

N:1
arb

Local Arbitration

per input port

V:1
arb

granted[i]

(c)

Fig. 8.3 The possible organizations for a combined allocator using ( a ) a VA1 module in series to