Baseline Virtual-Channel Based Switching Modules and Routers - Microarchitecture of Network-on-Chip Routers - page 113

outVCAvailable

per input VC

V

VCgranted[i]

per output VC

selOutVC[i]

V

V:1
arb

NV:1
arb

reqVC[i]

V V

V

V

NV:1
arb

V:1
arb

V V V

total NV
V:1 arbiters

total V
NV:1 arbiters

Fig. 7.5 The organization of a VC allocator for a many-to-one connection. In VA1, each input VC
independently selects to request one of the available output VCs. Then, after VA2, each output VC
selects to which input VC will be allocated

output VC availabilities should be performed first, before any arbitration occurs. The
first arbitration, called VA1, is done per input VC with the goal to select the output
VC that each input VC will finally ask for, thus limiting potential requests for output
VCs to only one. Since the first stage of arbitration is done independently per input
VC, many VCs may select the same output VC. As a result, a second arbitration
step is required, called VA2, which is performed per output VC, selecting only one
input VC to match the corresponding output VC. The organization of this two-step
allocation process between input and output VCs is shown in Fig. 7.5 .
The VC allocator in the case of a many-to-one connection includes a V W 1
arbiter per input VC and a N V W 1 arbiter per output VC, as shown in Fig. 7.5 .
The selected output VC ( selOutVC Œi )forthei th input VC is decided during VA1.
If the selected output VC is indeed allocated to the i th input VC, is revealed by
VCgranted Œi that is produced after reorganizing the results of the output VC arbiters
and gathering the grants that correspond to the same input VC using a wide OR gate.
An example of the operation of the VC allocator, showing also the intermediate
grants produced by the VA1 stage of arbitration, is shown in Fig. 7.6 . Please notice
that since VC allocation is done independently for each input VC, it is possible that
multiple VCs of the same input to allocate an output VC in the same cycle. In the
example shown in Fig. 7.6 VC#1 and VC#2, that both belong to input 0, are matched
to output VC#2 and VC#0 respectively in the same allocation round.