Baseline Virtual-Channel Based Switching Modules and Routers - Microarchitecture of Network-on-Chip Routers - page 106

Chapter 7
Baseline Virtual-Channel Based Switching
Modules and Routers

In this chapter we describe the operation and the microarchitecture of a virtual
channel based router by analyzing in detail the subtasks involved, the dependencies
across these tasks, and the extra state needed for their implementation. This chapter
covers single-cycle implementations of virtual-channel-based routers, while high-
speed alternatives and pipelined organizations are left for the following chapters.
Every router should support arbitrary connections between inputs and output ports
that connect to independently flow-controlled links. The links in this case host many
virtual channels (VCs) that are interleaved in a time-multiplexed manner.
We start our discussion on the implementation VC-based switching by describing
the organization and the operation of a many-to-one connection that connects many
input links to one output link that each one supports a set of virtual channels. Then,
we generalize this design to a complete VC-based router that supports many-to-
many connections, while still allowing the existence of many VCs in parallel.

7.1 Many to One Connection with VCs

The abstract organization of a many-to-one connection that supports multiple VCs
at the input and the output channels is shown in Fig. 7.1 . Each input is equipped with
as many parallel buffers as the number of VCs. The switching module connects the
input VC buffers to a single output via a simple physical link. The flits passing from
the output of the switching module should be placed to a buffer that corresponds to
the VC that they belong to. The parallel output VC buffers can be placed either at the
output of the switching module or at the other side of the link. In this configuration
we chose to include the output VC buffers at the other end of the link, and include
at the output of the switching module only a pipeline register that just isolates the
internal timing paths of the switching module from the link. Even if the output VC
buffers are placed far from the output of the switching module, any state variables