PipelinedWormhole Routers - Microarchitecture of Network-on-Chip Routers - page 86

0 1 2 3 4 5 6 7 8 9

cc
s SA

H LT-BW RC DQ-ST LT-BW

cc
SA -DQ-ST B LT-BW LT-BW

su

cc
SA -DQ-ST

T LT-BW LT-BW

su

cc
s SA

H LT-BW RC DQ-ST LT-BW

Fig. 5.16 The flow of flits in a 3-stage pipelined router where pipelining is employed only in the
control path of the RC and SA stages

The organization of the router is just a composition of the RC control-only
pipeline stage, shown in Fig. 5.4 ,wherethe outPort register acts as the pipeline
register and SA control pipeline stage of Fig. 5.11 , where the grants are stored at the
output of the SA and re-used by the body and tail flits of the packet.
First of all, since only one flit can deliver its control information per input (only
one in the frontmost position of the input buffer), there should be at least one idle
cycle between consecutive packets, as depicted in Fig. 5.16 . This is revealed in cycle
5 where the head flit of the second packet waits unnecessarily for the tail flit to leave
the input buffer and complete RC in cycle 6, although it actually arrived at the input
of the router in cycle 3. Besides that, the rest flits experience an un-interrupted flow.
For example the body and tail flits re-use in cycles 4 and 5 the grants returned to
their input in cycle 3 after the request generated in cycle 2 by the head flit of the
same packet.

5.4.2 Pipelining the Router in the Control and the Datapath

The idle cycles can be removed by employing combined control and data pipelines
for both the RC and the SA stage. The organization of the router that employs
this pipelined configuration is shown in Fig. 5.17 . By observing closely the block
diagram of Fig. 5.17 , we can see that the organization presented is derived by
stitching together the RC and SA combined pipelines presented in Figs. 5.7 and 5.13 ,
respectively.
The pipelined operation experienced by the flits of a certain input that belong to
two consecutive packets is shown in Fig. 5.18 . The first flit (head flit) that arrives
in cycle 0 will leave the router four cycles later. In cycle 1 it completes routing
computation and at the end of the cycle it moves to the pipelined EB of the RC stage.
This movement required the dequeue of the head flit from the input buffer. In cycle
2, the requests stored in the outPort pipeline register are sent to SA that returns the
corresponding grants in the same cycle. These grants are used to dequeue the head
flit from the intermediate EB and place it to the pipeline register at the input of the
crossbar. In the meantime, the body flit of the same packet has arrived and moved
to the intermediate EB. During cycle 3 the head flit just moves through the crossbar