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8. Some computer architectures include an immediate operation of the form
op $reg1,$reg2,val
that computes $reg1 = $reg2 op val. In an immediate instruction, val
does not need to be loaded into a register; it is extracted directly from
the instruction's bit pattern.
Explain how to extend
register
N
eeds
and
tree
CG to accommodate ar-
chitectures that include immediate operations.
9. Sometimes the code generated for an expression tree can be improved
if the associative property of operators like + and * is exploited. For
example, if the following expression is translated using
tree
CG, four
registers will be needed:
(a+b) * (c+d) * ((e+f) / (g-h))
Even if the commutativity of + and * is exploited, four registers are still
required. However, if the associativity of multiplication is exploited to
evaluate multiplicands from right to left, then only three registers are
needed. First ((e+f)/(g-h)) is evaluated, then (c+d)*((e+f)/(g-h)),
and finally (a+b)*(c+d)*((e+f)/(g-h)).
Write a routine
that reorders the operands of associative op-
erations to reduce register needs. (Hint: Allow associative operators to
have more than two operands.)
associate
10. In Section 13.4 we saw that many modern architectures are
delayed load
.
That is, a value loaded into a register may not be used in the next in-
struction; a delay of one or more instructions is imposed (to allow time
to access the cache).
The
CG routine of Section 13.2 is not designed to handle delayed
loads. Hence, it almost always generates instruction sequences that stall
at selected loads.
Show that if an instruction sequence (of length 4 or more) generated by
tree
tree
CG is given an additional register, it is possible to reorder the gener-
ated instructions to avoid all stalls for a processor with a one instruction
load delay. (It will be necessary to reassign the register used by some
operands to utilize the extra register.)
