Java Reference
In-Depth Information
ldc IntLit1
{Bytecode
sequence
for operand}
ldc IntLit3
iadd
{Bytecode
⇒
sequence
for operand}
⇒
ldc IntLit1
ldc IntLit3
n
ldc IntLit2
iadd
ldc 2
ldc n
ishl
iadd
ldc IntLit2
iadd
⇒
imul
(a)
(b)
(c)
⇒
ldc IntLit
ldc IntLit
ldc IntLit1
ldc IntLit
iconst_1
imul
⇒
ldc IntLit
⇒
ldc IntLit2
ldc IntLit1
iconst_0
ldc IntLit2
iadd
iadd
iadd
(d)
(e)
(f)
ldc IntLit1
ldc IntLit2
ineg
iadd
⇒
ldc IntLit1
ldc IntLit2
isub
(g)
Figure 13.33: Bytecode-Level Peephole Optimizations
As illustrated in Figure 13.33, optimizations corresponding to those of
Figure 13.32 can be applied to a bytecode representation of a program. This
level of optimization may be appropriate if bytecodes are later expanded into
target machine code. Alternatively, the machine-level optimizations described
in the next section may be applied to bytecodes, since bytecodes share much
of the structure of conventional machine code.
Code-Level Optimizations
Figure 13.34 illustrates some simple peephole optimizations performed after
code generation. In (a) a conditional branch around an unconditional branch is
replaced with a single conditional branch (with the sense of the test inverted).
In (b), a branch to the next instruction is removed (this is sometimes generated
when a
then
or
else
part of an
if
is null). A branch to a second branch can be
collapsed to a direct branch to the final target (c). In (d), a move from a register
to itself is suppressed (this sometimes happens when a special register, such
as a parameter register, is loaded with a value that already is in the correct
register). In (e), a register is stored into a location and then that same register
is immediately reloaded from the same location; the load is unnecessary and
may be deleted.
More elaborate architectures present additional opportunities for peephole
optimization. If a special increment or decrement instruction is available, it
can replace an ordinary add-immediate instruction (which usually is longer
and a bit slower). If auto-increment or auto-decrement addressing modes are
available, these can subsume an explicit increment or decrement of an index.
Some architectures have a special
loop control instruction
that decrements a
