Hardware Reference
In-Depth Information
0
10
30
50
70
90
110
130
150
170
190
clk
a
b
Fig. 4.10
Timing diagram for assertion a2
explicitly by calling system function $sampled in the action blocks, as explained
in Sect. 7.2.1.1 .
Example 4.7. Below, we reuse the example from Sect. 4.2.1 by substituting imme-
diate assertion by a concurrent one.
a2: assert property (@( posedge clk)a==b)
begin
a2_success++;
$info("a2: a and b have value %b", a);
end
else begin
a2_failure++;
$error("a2 failure: a = %b,b=%b",a,b);
end
The timing diagram with the addition of the clk waveform is reproduced in
Fig. 4.10 .
The pass action of assertion a2 executes at times 10, 30, 50, 70, 90, 170, and
190. Its fail action executes at times 110, 130, and 150. As an example, consider
assertion status at time 90. Assertion a2 samples values of signals a and b in the
Preponed region, that is before the value of a changes. Both a and b at time 90
have the sampled value 1, the assertion passes at that time, and its pass action
is executed; counter a2_success is incremented by one, and the message a2: a
and b have value 0 is printed. Yes, it is 0 that is printed, not 1 because the
action blocks of concurrent assertions are executed in the Reactive region, and
the value of a there is already 0. The message is misleading, since the assertion
uses the old value of a , while its action block uses the new one! To correct this,
we should explicitly specify the sampled values of a and b in the action blocks:
$info("a2: a and b have value b", $sampled(a)) in the pass action block,
and $error("a2 failure:a=%b,b=%b",$sampled(a), $sampled(b))
in the fail action block.
t
There are several exceptions to the general rule of sampling signal values in
concurrent assertions, such as the sampled values of automatic variables, local
variables and active free checker variables, and in common assertion usage the
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