Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 72

10 20 30 40 50 60 70 80 90 100

clk

a

Fig. 4.7 Signal glitches

10 20 30 40 50 60 70 80 90 100

clk

en

a

Fig. 4.8 Gated clock

The clocking event follows standard SystemVerilog semantics, and it
is based on the clock signal changes: posedge clk triggers when clk becomes
1, negedge clk triggers when clk becomes 0, clk triggers any time when clk
changes value, and edge clk triggers when clk changes to 0 or to 1. 4
For example, the assertion

a2: assert property (@clk a);
does not mean that a is checked each time when clk is high, but rather each time
when clk changes.

Gated Clock

An assertion clock may be gated. For example, the following assertion has a gated
clock which is active only when en is high:
a3: assert property (@( posedge clk iff en) a);
When en is low clock ticks are ignored. For example, this assertion passes in the
case shown in Fig. 4.8 because clk is disabled while a is low until time 55.

4 clk and edge clk behave the same way when clk is of type bit , but they behave differently
when the type is logic .