Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 61

Immediate assertions are sensitive to simulation glitches. Use them only when
you need to follow exactly the simulation flow, in program -based testbenches,
or when your code contains delay controls. In all other cases when unclocked
Boolean assertions are required use deferred assertions.

4.2.3 Effect of Short-Circuiting

Immediate assertions (simple and deferred) can be placed in functions. Functions
can be called in expressions involving logic operators. This may lead to some
unexpected results because of short-circuiting in the evaluation of the expressions.
Consider the following example:

function bit check3bits ( bit [2:0] expr, value);
a2: assert (expr > value) else
$error("a2 failure: expr = %b, value = %b", expr, value);
return (expr > value);
endfunction : check3bits
assign combined = v && check3bits(x, 3'b1);
Suppose that both v and x become 0 at some simulation time step. The continuous
assignment is evaluated, but since the first operand v of && is 0 , the simulator
determines that combined is 0 and by the rule of short-circuiting it does not need
to evaluate the function call. Therefore, the assertion is not evaluated either and the
error goes undetected. If the order of operands in the assignment were exchanged, as
in assign combined = check3bits(x, 3'b1)&& v; the error would be detected
because the first operand is always evaluated. A similar situation can arise when &&
is replaced by || and v takes the value of 1 .

4.3 Deferred Assertions

The official name of deferred assertions is “deferred immediate assertions” since
they are a variant of immediate assertions. However, we will call them simply
“deferred assertions”, reserving the name “immediate assertions” for immedi-
ate assertions that are not deferred.
Deferred assertions are unclocked Boolean assertions, and they differ from
immediate assertions in the following ways:

￿ Deferred assertions come in two forms identified by the keywords assert #0
for observed deferred assertions and assert final for final deferred assertions .
In the rest of the topic we refer to the latter simply as final assertions .
￿ Deferred assertions are not sensitive to simulation glitches.
￿ Deferred assertions may be placed both inside and outside procedural code.