Assertion Statements - SVA: The Power of Assertions in SystemVerilog - page 59

Fig. 4.2 Immediate assertion

0 10 30 50 70 90 110 130 150 170 190

a

b

Fig. 4.3 Timing diagram for assertion a1

in the Reactive region (Sect. 3.5 ). Immediate assertions in programs and checkers
execute in the Reactive region. 2
Figure 4.2 contains an example of immediate assertion a1 , and the corresponding
timing diagram for the values of its expression variables is shown in Fig. 4.3 . Recall
(Sect. 2.2.1.1 ) that the always_comb procedure executes unconditionally at time 0,
and note that at time 0 both a and b have the value 1'b0 . Therefore, the pass action
is executed at time 0. The pass action increments counter a1_success and prints
a message a1: a and b have value 0 . Because always_comb is sensitive to
the arguments of assertion a1 , each time the value of either a or b changes, a
reevaluation of the assertion condition is prompted, followed by the execution of
the appropriate action block. Thus, the pass action is executed at time 50, 150, and
190, while the fail action block is executed at 90.
In practice, the pass action of assertions is seldom used as assertions are expected
to succeed. The success information may provide confidence at the beginning of
design and test development, but quickly becomes superfluous later on. The most
common way is to specify only a fail action to issue an error message:

a1: assert (a == b)
else $error("a1 failure:a=%b,b=%b",a,b);

2 The LRM contains contradictory text that should be resolved in the subsequent revision: In Clause
17.5 it states that initial procedures in checkers can contain immediate assertions, but in Clause 17.2
it does not allow immediate assertions in checker body.