SystemVerilog Simulation Semantics - SVA: The Power of Assertions in SystemVerilog - page 54

The time advances only when the events of the current time slot are exhausted.

3.7 Simulation Semantics of Assignments

We briefly review the impact of assignments on scheduling events. We assume that
the assignments are executed in the Active region set. This happens, for example,
for assignments belonging to a module. The same rules apply to assignments
belonging to a program with an only difference that they are executed in the Reactive
region set.

￿ A continuous assignment schedules an update event in the Active region to update
the value of its left-hand side, whenever there is a change in the right-hand side
expression value.
￿ A blocking assignment without a delay executes immediately, and issues update
events for statements dependent on the new value of the left-hand side. An
assignment with 0 intra-assignment delay computes the right-hand side and
schedules an evaluation event in the Inactive region to make the assignment, issue
other update events if necessary, and continue the sequential execution from that
statement. For a greater delay, it schedules like for 0 delay in the Active region
for the future time.
￿ A nonblocking assignment schedules an update event in the NBA region to update
the left-hand side based on the current value of the right-hand side. For a delayed
statement, it schedules the event for a future time in the NBA region based on the
delay.

The event processing rules discussed in this chapter apply to the Active and
Reactive regions as explained with the use of their corresponding queues. In
the Observed region, only certain special statements are executed. Largely, the
evaluation of concurrent assertions is carried in the Observed region. Chapters 4
and 14 discuss assertion simulation semantics in more detail.