SystemVerilog Simulation Semantics - SVA: The Power of Assertions in SystemVerilog - page 44

Example 3.1. The module procReq contains a series of assignments:

1 module procReq( input logic req, gnt1, gnt2, clk);
2 wire tmp, proceed;
3 logic allow;
4 assign tmp = allow & gnt1;
5 assign proceed = tmp & gnt2;
6 always @( posedge clk) allow <= req;
7 always @( posedge proceed) processData();
8 endmodule : procReq

Assuming that input clk transitions from 0 to 1 and no other input changes at
that time, the result would be as if the following evaluation order were imposed:

1. Assignment to allow in Line 6

2. Assignment to tmp in Line 4

3. Assignment to proceed in Line 5

4. Evaluation of the subroutine (task or function) processData if proceed

becomes true in Line 7

As we will see in this chapter, this order of evaluation is obtained by creating
events, scheduling events, and performing the computations directed by the sche-
duled events, all carried out in the order established by the semantic framework to
obtain the intended result. The parallelism between the continuous assignments and
always statements in this example is broken down into ordered discrete events. Thus,
in this case, the parallelism is unrolled into a sequential order as directed by the
occurrence of events. In other cases, true parallelism may exist between statements,
allowing indeterminate order of statement execution and values of variables.

t

Another important facet of SystemVerilog is Programming Language Interface
(PLI) (or its newer version VPI) described in the LRM, which provides an interface
from the evaluation of language constructs to the external environment using other
programming languages or scripts. The interface is used to inspect values, change
values or get callbacks. There are certain points in the semantic structure where
specific groups of VPI functions are allowed to take place. We, however, do not
delve into the details of that allotment. The rest of the semantics are largely
unaffected by its exclusion.

3.2 The Simulation Engine

There are two types of events that help explain the event-driven simulation engine:
update event and evaluation event . This notion of event should not be confused with
event construct in SystemVerilog which is a data type used to name and trigger
events. An update event occurs whenever there is a change in the value of a variable.
The update event may trigger other activities and events dependent on the change in
value.