Hardware Reference
In-Depth Information
Chapter 3
SystemVerilog Simulation Semantics
Imitation is at least 50 percent of the creative process.
—
Jamie Buckingham
In this chapter we discuss SystemVerilog simulation semantics: how the
SystemVerilog model simulation is performed. This is necessary to understand
the simulation semantics of assertions described further in this topic. We cover
simulation semantics of the language features only as needed to provide a frame of
reference for completing the discussion on semantics of assertions. The exhaustive
description of SystemVerilog simulation semantics may be found in the LRM. See
also topics [
59
,
61
].
3.1
Event Based Simulation
SystemVerilog constructs do not exist in isolation and the interaction between them
in simulation is rather complex. The description of their behavior in simulation is
known as the
simulation semantics
of the language. The simulation semantics of
SystemVerilog is described in terms of
events
and processes. Examples of processes
are structured procedures (initial and all kinds of always procedures, see Sect.
2.2.1
),
continuous assignments, etc. All processes are scheduled concurrently, i.e., they
may be executed in parallel. However, in many cases the result of process evaluation
should be such as if a specific order of process evaluation were imposed.
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