SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 39

typedef enum logic {REQ = 1'b1, ACK = 1'b0} dirType;

typedef struct packed {
dirType rq;
logic [6:0] id;
logic [23:0] data;
} packetType;

program test ( input logic clk, packetType received,
output packetType sent);
logic [6:0] sent_id;
initial begin
repeat (100) begin
@( posedge clk);
sent_id = $random;
sent = '{REQ, sent_id, $random};
@( posedge clk);
a1: assert final (received.rq == ACK)
else $error("Corrupted packet");
a2: assert final (received.id == sent_id)
else $error("Lost packet");

end
end
endprogram : test

module router ( input packetType inpkt, logic clk,
output packetType outpkt);

...
endmodule : router
module top;
logic clk = 1'b0;
initial repeat (400) #5 clk = !clk;
packetType inpkt, outpkt;
test t(.clk(clk), .received(outpkt), .sent(inpkt));
router r(. * );
endmodule : top
Program test checks also the correctness of the received packets. Assertion
a1 checks that the received packet is an acknowledgment packet, and assertion
a2 checks that the ID of the acknowledgment packet coincides with the ID of the
request packet sent in the previous cycle. t

2.6 Packages

The design element package is intended for encapsulation and reuse of common
declarations. One can use packages as libraries of useful declarations, such as type
definitions, function, task, let declarations, properties, sequences, and checkers.
A package introduces its own name space to avoid conflicts with local names where
a package element is referenced.