References - SVA: The Power of Assertions in SystemVerilog - page 561

41. J. Havlicek, K. Shultz, R. Armoni, S. Dudani, E. Cerny, Accellera Technical Report 2004.01:
Notes on the Semantics of Local Variables in Accellera SystemVerilog 3.1 Concurrent
Assertions, May 2004
42. S. Hazelhurst, O. Weissberg, G. Kamhi, L. Fix, A hybrid verification approach: getting deep
into the design, in DAC '02: Proceedings of the 39th Conference on Design Automation (ACM,
New York, 2002), pp. 111-116
43. J.L. Hennessy, D.A. Patterson, Computer Architecture, Fourth Edition: A Quantitative
Approach . (Morgan Kaufmann Publishers Inc., San Francisco, 2011)
44. C.R. Ho, M. Theobald, B. Batson, J. Grossman, S.C. Wang, J. Gagliardo, M.M. Deneroff, R.O.
Dror, D.E. Shaw, Four pillars of assertion-based verification, in Proceedings of the Design and
Verification Conference and Exhibition (San Jose, 2009)
45. A. Kuehlmann, C.A.J. van Eijk, Combinational and sequential equivalence checking, in Logic
Synthesis and Verification (Kluwer Academic Publishers, Norwell, 2002), pp. 343-372
46. O. Kupferman, M.Y. Vardi, Model checking of safety properties. Form. Methods Syst. Des.
19 (3), 291-314 (2001)
47. O. Kupferman, M.Y. Vardi, Vacuity detection in temporal model checking. Int. J. Softw. Tools
Technol. Transfer 4 (2), 224-233 (2003)
48. L. Lamport, Specifying Systems, The TLA+ Language and Tools for Hardware and Software
Engineers . (Addison-Wesley, Boston, 2002)
49. S. Malik, A case for runtime validation of hardware, in Haifa Verification Conference , Lecture
Notes in Computer Science. ISBN 978-3-540-32604-5, pp. 30-42 (Springer, 2006)
50. Microsoft Research, AsmL: Abstract State Machine Language (2001), http://research.

microsoft.com/en-us/projects/asml
51. S.S. Muchnick, Advanced Compiler Design and Implementation . (Morgan Kaufmann, San

Francisco, 1973)
52. R. Mukhopadhyay, S.K. Panda, P. Dasgupta, J. Gough, Instrumenting ams assertion verification
on commercial platforms. ACM Trans. Des. Autom. Electron. Syst. 14 (2), 1-47 (2009)
53. The Open Group, Assertion Definition Language (2009), http://adl.opengroup.org/about/index.
html
54. R.H. Parker. Caution: clock crossing. a prescription for uncontaminated data across clock
domains. Chip Design Magazine 5 April 2004
55. M. Pellauer, M. Lis, D. Baltus, R. Nikhil, Synthesis of synchronous assertions with guarded
atomic actions, in 2nd ACM/IEEE International Conference on Formal Methods and Models
for Co-Design , (IEEE Computer Society, Washington, 2005), pp. 15-24
56. R.B. Reese, M.A. Thornton. Introduction to Logic Synthesis Using Verilog HDL (Synthesis
Lectures on Digital Circuits and Systems) (Morgan and Claypool, San Rafael, 2006)
57. H. Rotithor, Postsilicon validation methodology for microprocessors. IEEE Des. Test, 17 (4),
77-88 (2000)
58. T. Schubert, High-level formal verification of next-generation microprocessors, in Proceedings
of the Design Automation Conference (IEEE/ACM, 2003), pp. 1-6
59. C. Spear, G. Tumbush. SystemVerilog for Verification: A Guide to Learning the Testbench
Language Features . (Springer, New York, 2012)
60. Sun Developer Network, Java Programming Language, Java Standard Edition 6 (2010), http://
java.sun.com/
61. S. Sutherland, S. Davidmann, P. Flake, SystemVerilog for Design: A Guide to Using System-
Verilog for Hardware Design and Modeling , 2nd edn. (Springer, New York, 2006)
62. D. Tabakov, M.Y. Vardi, G. Kamhi, E. Singerman, A temporal language for SystemC,
in FMCAD '08: Proceedings of the 2008 International Conference on Formal Methods in
Computer-Aided Design , (IEEE Press, Piscataway, 2008), pp. 1-9
63. B.A. Trakhtenbrot, B.I.A. Finite Automata: Behaviour and Synthesis (North-Holland Publish-
ing Co., Amsterdam, 1973)
64. F. Vahid, Digital System Design with SystemVerilog , 2nd edn. (Wiley (1000), New York, 2010)
65. I. Wagner, V. Bertacco, Reversi: Post-silicon validation system for modern microprocessors, in
IEEE International Conference on Computer Design, 2008 (IEEE, 2008), pp. 307-314