Hardware Reference
In-Depth Information
References
1. IEEE Std. 1364-2001, IEEE Standard Verilog Hardware Description Language (2001)
2. IEEE Std. 1364-2005, IEEE Standard Verilog Hardware Description Language (2005)
3. IEEE
Std.
1800-2005,
IEEE
Standard
for
SystemVerilog—Unified
Hardware
Design,
Specification, and Verification Language (2005)
4. IEEE Std. 1076-2008, IEEE Standard VHDL Language Reference Manual (2008)
5. IEEE Std. 1800-2009, IEEE Standard for SystemVerilog—Unified Hardware Design, Specifi-
cation, and Verification Language (2009)
6. IEEE Std. 1850-2010, IEEE Standard for Property Specification Language (PSL) (2010)
7. IEEE Std. 1666-2011, IEEE Standard SystemC R
Language Reference Manual (2011)
8. IEEE Std. 1800-2012, IEEE Standard for SystemVerilog—Unified Hardware Design, Specifi-
cation, and Verification Language (2012)
9. Accellera. Universal Verification Methodology (UVM) 1.1 (2011)
10. Accellera. Accellera Standard Open Verification Library (OVL) V2.8 (2013)
11. A. Adir, S. Copty, S. Landa, A. Nahir, G. Shurek, A. Ziv, C. Meissner, J. Schumann, A unified
methodology for pre-silicon verification and post-silicon validation, in Proceedings of Design,
Automation and Test in Europe Conference and Exhibition (DATE), 2011 (IEEE, 2011), pp. 1-6
12. R. Armoni, L. Fix, A. Flaisher, R. Gerth, B. Ginsburg, T. Kanza, A. Landver, S. Mador-
Haim, E. Singerman, A. Tiemeyer, M.Y. Vardi, Y. Zbar, The ForSpec temporal logic: a new
temporal property-specification language, in TACAS'02: Proceedings of the 8th International
Conference on Tools and Algorithms for the Construction and Analysis of Systems (Springer,
London, 2002), pp. 296-211
13. R. Armoni, L. Fix, A. Flaisher, O. Grumberg, N. Piterman, A. Tiemeyer, M.Y. Vardi, Enhanced
vacuity detection in linear temporal logic, in Proceeding of International Conference on
Computer-Aided Verification , Lecture Notes in Computer Science. ISBN 3-540-40524-0,
pp. 368-380 (2003)
14. R. Armoni, S. Egorov, R. Fraer, D. Korchemny, M. Vardi, Efficient LTL compilation for SAT-
based model checking,
in IEEE/ACM International Conference on Computer-Aided Design
(IEEE, 2005)
15. P. Ashar, S. Dey, S. Malik, Exploiting multicycle false paths in the performance optimization
of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integrated Circ. Syst. I 14 (9),
1067-1075 (1995)
16. M.A. Azadpour, SystemVerilog for Design and Verification Using UVM: From RTL to Synthesis
(Springer, New York, 2013)
17. A. Aziz, J. Kukula, T. Shiple, Hybrid verification using saturated simulation, in Proceedings
of the Design Automation Conference , pp. 615-618 (IEEE and ACM, 1998)
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