SystemVerilog Language Overview - SVA: The Power of Assertions in SystemVerilog - page 37

Example 2.9. Consider two modules: producer and consumer . Their communica-
tion is implemented via interface data .

1 interface data ( input logic clk);
2 logic [7:0] a, b;
3 logic active_a, active_b;
4 endinterface : data
5
6 module producer (data i);
7

initial begin

i.active_a = 1'b1;

8

i.active_b = 1'b0;

9

end

10

always @( posedge i.clk) begin

11

i.active_a <= !i.active_b;

12

i.active_b <= !i.active_a;

13

i.a <= $random;

14

i.b <= $random;

15

16 end
17 endmodule : producer
18
19 module consumer (data i, output logic [7:0] out);
20 always @( posedge i.clk) begin
21 if (i.active_a) out <= i.a;
22 if (i.active_b) out <= i.b;
23 end
24 endmodule : consumer
25
26 module top;
27 logic clk=0;
28 logic [7:0] result;
29 initial repeat (100) #5 clk = !clk;
30 data ifc(clk);
31 producer prod(.i(ifc));
32 consumer cons(.i(ifc), .out(result));
33 endmodule : top

In this example interface data (Lines 1 - 4 ) is just a collection of signals. The
values of these signals are generated by the module producer (Lines 6 - 17 ) and
then the values of a and b are routed to the output by the module consumer
(Lines 19 - 24 ). These modules and the interface are instantiated in module top
(Lines 26 - 33 ). Instead of individual signal and port declarations for a , b , active_a
and active_b in the modules, all these declarations are packed in the interface.
Individual signals from the interface are accessed directly from the interface
instance.

t

Interfaces are a natural place to put assertions or to instantiate checkers to
specify the obligations imposed on the modules on one side of the interface and the
expectations of the modules on its other side (see Sect. 1.2.2 ). This allows to avoid
duplication from specifying the same assertions at the boundaries of each connected
module.