Hardware Reference
In-Depth Information
Chapter 24
Checker Libraries
A room without topics is like a body without a soul.
G.K. Chesterton
The enhancements to the IEEE SystemVerilog language in the 2009 and 2012
standards and, in particular, to the SystemVerilog Assertions (SVA) allow us to
create much more useful and versatile checker libraries. In this chapter, we first
identify the weaknesses of the current checker libraries by examining an example
from the OVL library. We then provide a classification of checkers , and show how
various forms of effective checker libraries can be created using the new constructs.
We use the term checker and checker library in a broad sense to denote a verification
unit and library, possibly assertion based. We refer to the SystemVerilog checker
construct using checker .
There are many functional properties common to any design that are reusable
modulo some expression changes. Therefore, to speed up the deployment of
assertions without requiring extensive knowledge of the syntax and semantics of
the SystemVerilog assertions language, it is essential to create libraries of checkers.
Such checker libraries have been around for some time, such as the Accellera Open
Verification Library (OVL) [ 10 ], and other checker libraries from EDA vendors.
A similar approach was used even before the arrival of assertion languages by
hiding procedural or RTL implementation of assertions in modules used as checkers.
The initial implementation as well as the Verilog'95 implementation of OVL is in
this form.
The enhancements to the SystemVerilog language in the 2009 and 2012 stan-
dards and, in particular to the assertion features allow us to create much more
useful and versatile checker libraries. They benefit primarily from the following
features: New encapsulation, let declarations, clock and disable inference, deferred
assertions, elaboration error tasks, and enhanced property operators. The new
checker encapsulation can be used to replace the module. These enhancements
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