Hardware Reference
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sampled, and when it is not. Hint: consider an assignment where the right-hand side
is a checker input argument whose actual value is generated in a module.
23.9. Why is a separate processing of a packet start (Line 13 )inFig. 23.5 required?
Why is this processing not subsumed by Lines 14 - 15 ?
23.10. Implement a packet transmission in checker tx from Sect. 23.5 using a shift
register instead of a pointer to a current bit (Fig. 23.5 , Lines 10 - 17 ).
23.11. Modify checker tx (Figs. 23.4 and 23.5 ) to support packet reception ack-
nowledgment: the generator should receive an acknowledgment ( ack asserted) from
the DUT within 4 clock cycles upon the packet transmission. In the absence of the
acknowledgment the same packet must be retransmitted. No new packet, but the
first one, may start transmission until the acknowledgment of the previous packet
reception has been obtained.
23.12.
Limit the number of retries described in Exercise 23.11 to 3.
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