Hardware Reference
In-Depth Information
2.3
Clocking Blocks
2.3.1
Clocking Block Declaration
The clocking block construct is aimed to provide a flexible scheme for synchronizing
and sampling of signals with respect to a design clock. Often the input signals
are driven from a testbench to design units, while the testbench is modeled by a
program (see Sect. 2.5 ). New values to signals for a test are set in the testbench with
appropriate delays using a clocking block.
It is possible to enclose property and sequence definitions in a clocking block,
using the common event control of the clocking block. This assists in grouping
related properties and sequences as well as it provides the convenience of leaving
out the explicit specification of a clock for each individual declaration of a property
or sequence in the clocking block.
For use of clocking blocks in testbenches, readers are advised to refer to topics
on SystemVerilog testbench (such as [ 59 ]) or to the LRM. Clocking declarations
may be included in modules, interfaces, programs and checkers. Along with other
information, a clocking block may be declared with
￿ A name
￿ An event expression
￿ Variables sampled and driven by the clocking block
￿ A list of sequences and properties
There is one restriction on the declarations of properties and sequences: no
explicit clock is allowed in the declarations. Consequently, multiply clocked
properties or sequences cannot be declared inside clocking blocks. Note also that
assertions cannot be written within a clocking block.
Example 2.7. The code below contains a clocking block named cblk declared with
the clocking event @( posedge clk) .
logic req, gnt;
// Evaluation of gnt
...
clocking cblk @( posedge clk);
input req, gnt;
property p_req_granted;
req |=> gnt;
endproperty
endclocking
a1: assert property (cblk.p_req_granted)
else $error("Request not granted");
a2: assert property (@( posedge clk) req |=> !req)
else $error("Request asserted during two consecutive cycles");
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